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Design

BottleneckCore: AI training, AI inference, Robotics, EV / auto, Consumer / IoT, Industrial

EDA software

China has partial domestic tools, but full-flow advanced-node EDA remains one of the hardest parts of the stack to replace.

The simple version

EDA is chip-design software. It is the software engineers use to design, verify, simulate, and prepare chips before they are manufactured.

What the technology does

  • Modern chips are too complex to design manually. EDA tools manage logic design, timing, power, verification, layout, and manufacturing rules.
  • The tools must work with process design kits. That makes trust and certification extremely important.
  • A partial tool can be useful, but frontier chips need full flows that work together reliably.

Market scale

  • Synopsys, Cadence, and Siemens EDA dominate the global market. Synopsys and Cadence each operate at multi-billion-dollar annual revenue scale.
  • EDA is small compared with chips, but strategically enormous because every advanced chip company depends on it.
  • The business is sticky: once a design team trusts a tool flow, switching is painful and risky.
Global references
  • SynopsysUnited States · SNPS
  • CadenceUnited States · CDNS
  • Siemens EDAGermany · SIE.DE
  • AnsysUnited States · ANSS

China angle

Empyrean, Primarius, Xpeedic, and Semitronix matter because they give China partial domestic options. The hard part is full-flow advanced-node coverage and customer trust, not a single isolated tool.

China references

How we got here

EDA grew alongside chip complexity from the 1980s onward. As export controls expanded, it became one of China's most visible software choke points.

  1. 1980s-1990s

    Commercial EDA becomes essential as chip designs outgrow manual methods.

  2. 2000s-2010s

    Synopsys, Cadence, and Mentor/Siemens consolidate the global toolchain.

  3. 2020s

    US restrictions make domestic EDA a Chinese strategic priority.

  4. Next phase

    Watch advanced-node support, certification, and whether top Chinese design houses migrate real projects.

Why it matters

No serious chip design happens without EDA. Restrictions here can slow the entire semiconductor stack.

Main bottleneck

Full-flow coverage, advanced-node validation, PDK integration, IP ecosystem, and decades of accumulated tool trust.

Where this sector shows up

Core
AI training, AI inference, Robotics, EV / auto, Consumer / IoT, Industrial

What to watch

  • Advanced-node support
  • certifications
  • IPO disclosures
  • Customer migration proof
  • US restriction scope