Company at a glance
Scale
Revenue up 31% since FY2023
Growth prospects
Expanding customer base and product roadmap
2024 revenue RMB 1,222,354,443.47 (+20.98% YoY); net profit RMB 109,478,790.34 (-45.46% YoY)China competition
Competes with Primarius, Xpeedic, Semitronix in EDA — peers listed at sector level.
BottleneckGlobal comparables
Global reference set: Synopsys, Cadence, Siemens EDA.
Synopsys, Cadence, and Siemens EDA are the global reference set.Technical gap
Sector rated bottleneck vs the frontier.
Obstacles
US export-control exposure
Added to the U.S. Entity List in December 2024.Official filings: static.cninfo.com.cn ↗
All sourced facts (8)
- Founded: Founded in 2009 and headquartered in Beijing.
- Headquarters: Beijing, China
- Revenue / scale: 2024 revenue RMB 1,222,354,443.47 (+20.98% YoY); net profit RMB 109,478,790.34 (-45.46% YoY)
- Listing status: Shenzhen Stock Exchange (SZSE) · 301269 · A-shares (stock abbreviation 华大九天)
- Listing: Listed on the Shenzhen Stock Exchange ChiNext board as 301269 in 2022.
- China EDA position: Reported as the largest domestic EDA player and about 6% of China's EDA market as of 2024, still far behind Synopsys, Cadence, and Siemens EDA globally.
- Tool coverage claim: Reported domestic EDA coverage includes analog tools with partial 5nm support and digital tools with 7nm support; full advanced-node signoff remains the hard question.
- Export controls: Added to the U.S. Entity List in December 2024.
About
Sells electronic design automation software and related services to IC design companies, foundries, and system-in-package design teams. Its strategic value is tool coverage and domestic workflow integration, not chip output.
Beijing · Founded 2009 · Ticker 301269
Why it matters
EDA is a small revenue pool compared with fabs or memory, but it controls whether designers can tape out chips without relying entirely on U.S.-linked design software. Empyrean is therefore a bottleneck company even if its financial scale is modest.
Where it sits in the stack
Key semiconductor products
- Analog IC design and simulation tools.
- Digital IC design and verification tools.
- Xpeedic-linked system-in-package and high-speed electromagnetic/signal-integrity design capability after the 2025 acquisition announcement.·2025
- Full-custom design platform·Aether, ALPS, Polas, Patron, Skipper
- Digital SoC EDA
- Foundry EDA·XModel, Demeter, Mage
- Advanced packaging EDA
- 3DIC EDA
- Flat-panel display EDA
- Foundation IP / PDK services
Financials
301269.SZ · Shenzhen ChiNext 301269 · via Yahoo Finance ↗
Financial trajectory via annual filings via Yahoo Finance
RMB billionsMarket data refreshed daily; annual figures from exchange filings. Figures in the reporting currency shown on the chart.
Ecosystem
Customers / end markets
- Diodes
- Will Semiconductor (韦尔股份)
- Hua Hong (华虹宏力)
- Ricoh Microelectronics (理光微电子)
- O2Micro (凹凸科技)
- HKC (惠科金渝)
- Chinese IC design houses, foundries, and state-backed semiconductor projects are the natural customer base
- Huawei-linked domestic EDA progress around 14nm-class design flows is a key signal to track, but individual customer claims should stay labeled unless sourced
Qualification sites
- Diodes
Partners
- CSOT (华星光电)
Global peer set
- Synopsys, Cadence, and Siemens EDA are the global reference set
- Ansys and Keysight matter for adjacent simulation and electromagnetic/signal-integrity workflows
Competitive position
- Empyrean should be treated as China's domestic EDA anchor, not as proof that China has closed the EDA gap.
- The useful topology view is tool-flow coverage: analog, digital front-end, verification, physical implementation, signoff, package/SIP, and foundry PDK integration.
- The strategic question is whether Chinese designers can use Empyrean inside real tapeout workflows, not whether a single tool demo supports a headline node.
- Broad domestic EDA coverage across analog, digital, foundry, packaging, and FPD flows; depth and signoff maturity versus global leaders not quantified in available sources.
- Credibility of foundry EDA line depends on cooperation with leading foundries/IDMs, which are not named in available sources.
- Global comparables: Synopsys, Cadence, and Siemens EDA are the global reference set.
- Global comparables: Ansys and Keysight matter for adjacent simulation and electromagnetic/signal-integrity workflows.
- EDA substitution depends on foundry PDK support, IP libraries, signoff trust, verification depth, and engineer workflow switching costs.
Recent activity
- 2025-04-28—Publication of 2024 annual report summary (announcement 2025-012) on CNINFO, reporting 2024 revenue RMB 1.222B (+20.98% YoY) and net profit RMB 109.5M (-45.46% YoY) [via static.cninfo.com.cn]
Milestones and signals
- 2009—Empyrean Technology was founded.
- 2026-10-04—Market cap: RMB 46.4B
- FY2025—Revenue: RMB 1.3B
- FY2025—Net Profit: RMB 61.0M
- Listing—Shenzhen Stock Exchange (SZSE) · 301269 · A-shares (stock abbreviation 华大九天)
What to watch
- 2024 Entity List impact and whether customer deployments slow or accelerate after U.S. restrictions.
- 2025 Xpeedic acquisition integration.
- Claims of 14nm, 7nm, or 5nm support should be separated into demo, partial flow, and production signoff.
- Market-share estimates within China versus actual global competitiveness.
Questions
Last reviewed 2026-07-01Answered questions
Which parts of the chip-design flow can Empyrean cover in production tapeouts: analog, digital, verification, physical design, signoff, packaging, or display?
On the record: Empyrean PDK services (Commercial use) at Multiple leading foundries/IDMs (unnamed) for Hundreds of PDKs including China's most advanced node and 28nm+ mature processes (logic, power, RF) and Empyrean Patron (Customer validation) at Diodes for Transistor-level power integrity analysis.
How much revenue is software license/subscription versus services/custom projects?
Against Synopsys, Cadence, and Siemens EDA are the global reference set and Ansys and Keysight matter for adjacent simulation and electromagnetic/signal-integrity workflows: Broad domestic EDA coverage across analog, digital, foundry, packaging, and FPD flows; depth and signoff maturity versus global leaders not quantified in available sources.
Does the Xpeedic acquisition fill a real packaging/SIP gap or mostly broaden the story?
Against Synopsys, Cadence, and Siemens EDA are the global reference set and Ansys and Keysight matter for adjacent simulation and electromagnetic/signal-integrity workflows: Broad domestic EDA coverage across analog, digital, foundry, packaging, and FPD flows; depth and signoff maturity versus global leaders not quantified in available sources.
Open questions
- Which foundries and process nodes have real PDK/tool qualification?