Specifications
Sourced specs
| Spec | Value | Source |
|---|---|---|
| Cores | Up to 80 cores (two 40-core Arm TaiShan compute chiplets); some Chinese teardown reports describe a 120-core (3-die) configuration | via techpowerup.com ↗2025-08-26 |
| Cache | ~91MB shared L3 per compute die; 2MB private L2 per core | via techpowerup.com ↗2025-08-26 |
| Memory | On-die DDR5 controllers, 12 channels per chiplet / up to 24 per CPU; photographed board routes 16 DIMM sockets | via techpowerup.com ↗2025-08-26 |
| I/O | Up to 96 PCIe lanes advertised; package ~77.5mm x 58.0mm | via techpowerup.com ↗2025-08-26 |
| 120-core report | Chinese teardown coverage reports 120 cores total (3 dies), 96 PCIe lanes, 16-channel DDR5, dual-socket platform, possibly 5nm | via news.mydrivers.com ↗2025-08 |
Pricing
Price history, newest first
No public price observation yet.
vendor-official or multiple independent reports · single major report or several secondary · estimate or lone secondary source
Prices in USD, converted at each observation year's average exchange rate; the original figure and rate print under every converted price. How prices are sourced and graded ↗
Context
Notes
- Pricing not publicly disclosed; chip itself not officially launched.
- All specs derive from the 'Kurnal' teardown (Aug 2025) relayed by TechPowerUp/EET-China; core-count reports conflict (80 vs 120).
- Successor Kunpeng 950 (up to 96 cores, first with Lingqu/灵衢 interconnect) announced March 2026 as ready for scale commercial use with TaiShan 950 SuperPoD (Guancha, 2026-03).
Where it sits
In the stack
All specs and prices link to their original sources, dated as observed. Figures are market observations, not offers; treat each as of its date.